1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly, to a method and software for generating enable and data input signals for flip-flops used for implementing complex logic functions on programmable logic devices.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs can generally also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs and reduced product development times makes the use of PLDs compelling for many OEMs.
Most PLDs contain a two-dimensional row and column based architecture to implement custom logic. A series of row and column interconnects, typically of varying length and speed, provide signal and clock interconnects between blocks of logic on the PLD. The blocks of logic, often referred to by such names as Logic Elements (LEs), Adaptive Logic Modules (ALMs), or Complex Logic Blocks (CLBs), usually include one or more look up table (LUTs), programmable registers, adders, flip-flops and other circuitry to implement various logic and arithmetic functions.
For example in the Stratix PLD from Altera Corporation of San Jose, Calif., each Logic Array Block or LAB includes eight (8) Logic Elements (LEs). Each LE includes a flip-flop that is used as a synchronous element that is capable of capturing a logic state of a signal. The LAB also includes two hardwire enable signals (ENA1 and ENA2) that are distributed throughout the LAB and that can be selectively used to enable the flip-flops in the LEs respectively. Alternatively, another logic signal, such as one of the outputs of a LUT, can be used to enable the flip-flop. Regardless of where the enable signal is derived, during operation the flip-flop latches data at its input and provides the data at its output. If the flip-flop is not enabled, then the output remains constant, regardless of any data transitions that may occur at the input. For more information on the Stratix architecture, see the Stratix Device Family Data Sheet, Chapter 2: “Stratix Architecture”, Ver. 3.3, July 2005, incorporated by reference herein for all purposes.
Programming software is typically used to program the PLDs. During logic design, the user is required to input the desired logic description into the programming software using a high level programming language, such as VHDL or Verilog. The software then synthesizes the high-level logic description into the needed basic logic components provided on the PLD, such as logic gates, flip-flops, and other logic constraints such as RAM, DSP, etc. During synthesis, the software also optimizes the design. Optimization involves finding the smallest, fastest and most power-efficient implementation of the logic design available on the PLD. The software next performs a place and route of the optimized logic design. Once the placement and routing is defined, the programming software generates a programming file which contains a plurality of bits used to program the PLD to implement the optimized logic function.
Since both VHDL and Verilog are behavioral languages, as opposed to structural languages, the description of the operation of a flip-flop is described in terms of a number of behavioral statements. For example, the code describing the operation of a flip-flop in Verilog can be represented as:                always@(posedge clock)        begin                    if(enable==1)                            output<=input;                                                endThe above Verilog code is interpreted as “if the enable input is a one (Vcc) on the positive edge transition of the clock, then the output equals the input”. This differs from a structural definition of a flip-flop, which would contain a specific list of inputs, outputs, enable and clock signals, etc., to the various ports of the device.        
Referring to FIG. 1, a circuit generated by the high level language defining the behavior of a flip-flop is shown. The circuit 10 includes a flip-flop 12 and a mux 14. The output of the mux 14 is provided to the D input of the flip-flop 12. The data output of the flip-flop 12 is provided to one input of the mux 14. A data signal 16 is provided to the other input of the mux 14. An enable signal ENA is provided to the select input 18 of the mux 14. When the ENA signal is high, the mux 14 provides the data input signal 16 to the D input of the flip-flop 12. Upon the next transition of clock CLK, the data signal is latched by the flip-flop 12 and provided at the Q output. If the ENA signal is low, the Q output signal is fed back to the input of flip-flop 12 through the mux 14. In this manner, the flip-flop is configured to retain its current value with each clock cycle while the ENA signal is low. Currently, the synthesis and place and route modules of most programming software packages used with PLDs would implement the flip-flop of FIG. 1 by using three input signals of a LUT in a logic element. For example, the data input signal 16, ENA signal 18, and Q output of the flip-flop 12 are all implemented using the input of the LUT. This means that only one of the four LUT input signals would be available for performing other logic. However, if the logic elements on the PLD had a hardwired enable signal available, the synthesis software could use the hardwire enable to simplify the circuit shown in FIG. 1.
Referring to FIG. 2, a circuit 20 of the simplified flip-flop using a hardwire enable is shown for the sake of illustration. The circuit 20 includes a flip-flop 22 with a data input 24, the hardwire ENA signal 24, and a clock signal CLK. The programming software optimizes the implementation of the flip-flop by taking advantage of and using the hardwire enable signal 26. The programming software implements this simplification by recognizing two characteristics of the circuit illustrated in FIG. 1. Namely, the software recognizes: (1) a two-to-one (2:1) mux feeding the data input of a flip-flop; and (2) one of the data inputs to the mux is an output of the flip-flop, creating a feedback loop. When both of these conditions are met, the programming software will recognize that the circuit is an enable flip-flop, and optimizes the circuit by using the hardware enable, removing the mux to implement the simplification.
The problem with existing programming software is that it is capable of performing the above-described optimization only in the most simple of situations. Generally speaking, the optimization can be performed only in cases where there is a single input, single enable flip-flop. In more complex situations, for example where a complex logic circuit is feeding a flip-flop, current programming software is unable to recognize that an optimization may be possible. As a result, the hardware enable is not used to simplify the logic. The complicated logic function and the flip-flop are therefore implemented using one or more LUTs which could otherwise be use to perform other logic functions. This shortfall typically results in an inefficient layout of the logic design, wasting resources on the PLD chip.
A method and software for generating enable and data input signals for flip-flops used for implementing complex logic functions on PLDs is therefore needed.